FIG. 4 is a block diagram of an example, conventional NOR flash memory device. As shown, a memory cell array MA may be configured with a plurality of word lines WL, a plurality of bit lines BL, and a plurality of transistors Tr (for example, floating gate field effect transistors) forming memory cells. The plurality of transistors Tr may be disposed at intersections of the word lines WL and the bit lines BL. Each of the transistors Tr may include a control gate, a drain, and a source connected to the word line WL, the bit line BL, and a ground line SL, respectively.
A source 106 and a drain 108 of the transistor Tr may be formed in a P-well 104 provided in an N-well 102 of a semiconductor substrate 100, as illustrated in FIG. 5.
A NOR flash memory may be structured such that the memory cells of MOS transistors having a stack gate structure are connected in parallel in a NOR type configuration.
As illustrated in FIG. 4, a row decoder RD may be provided for selecting word lines WL0 through WL1023 of the memory cell array MA, and a column decoder CD may be provided for selecting bit lines BL0 through BL511. Addresses may be transmitted to the row decoder RD and the column decoder CD as internal row address signals and internal column address signals, respectively, through an address control circuit (not shown). Based on a command decoded by a controller (not shown), sequence control including programming and erasing of data may be performed.
A negative voltage boosting circuit 20 may be connected to the row decoder RD through a negative voltage switch 10. The negative voltage boosting circuit 20 may generate a boosted voltage used in programming or erasing data. For example, the boosted voltage may be obtained by boosting a power supply voltage Vcc. A positive voltage boosting circuit 70 may be further provided in the flash memory because a boosted positive voltage may also be used in programming or erasing data. The boosted positive voltage may be supplied to the ground line SL or the P and N-wells 104 and 102 through a source-well voltage control circuit 60.
In addition, a source switch 30 may control connection/disconnection between the source-well voltage control circuit 60 and the ground line SL. Furthermore, a well switching unit 80 having a P-well switch 40 and an N-well switch 50 may control connection/disconnection between the P and N-wells 104 and 102 and the source-well voltage control circuit 60.
FIG. 6 is a plane view illustrating a cell array structure of an example NOR flash memory. FIG. 7 is a sectional view illustrating the structure of the example NOR flash memory of FIG. 6 taken along line X-X′.
As transistors in memory cells progressively shrink in size, capacitances between respective nodes of the memory cells may be changed. For example, the capacitance between a word line connected to a control gate and a bit line connected to a drain may become significantly higher than capacitances of other nodes because the space between a bit line contact and the word line may be reduced.
FIG. 8 is a timing diagram illustrating voltages applied during an erase operation performed in the flash memory device of FIG. 4. An example erase operation will be described below.
The power supply voltage Vcc may be applied to a word line of a cell in a neutral state. At this point, the bit line BL, the ground line SL, the P-well and the N-well may each be grounded. The word line voltage may be set equal to the ground voltage so that a sector including cells to be erased may be unselected. This state may be denoted as ERS set in FIG. 8. A voltage boosted to a level in the range of approximately 5V to approximately 9.5V by the positive voltage boosting circuit 70 of FIG. 5 may be applied to the P-well 104 and the N-well 102 for well charge.
It may take a given amount of time for the voltage to be boosted to reach the voltage level in the range of approximately 5V to approximately 9.5V, and the boosting operation may be performed so that the voltage may gradually increase from the ground voltage level Gnd to reach the voltage level in the range of approximately 5 to approximately 9.5V.
At this point, the ground line SL and the bit line BL, which may be connected to the source and the drain of the memory cell, may be opened, and the PN junction between the substrate and the source and drain regions may be forward biased. Therefore, a current may flow from the substrate to the source and the drain, and a voltage, which may be reduced from the above boosted voltage by a forward bias voltage Vf of the PN junction, may be applied to the bit line BL and the ground line SL.
Subsequently, the negative voltage boosting circuit 20 may operate so that a negative voltage of approximately −9V may be applied to the word line though the row decoder RD. Thus, an erase operation may be performed such that charges accumulated in a floating gate FG of the cell transistor Tr may be put into the semiconductor substrate.
After erasing, a word line discharge and a well discharge may be performed for discharging the negative and positive voltages applied during the erase operation to the ground voltage level. For a word line discharge, the word line may be grounded so that the charges accumulated in the word line are discharged. After the word line discharge, the bit line, the ground line, the P-well and the N-well may be grounded for performing the well discharge. Therefore, charges in the bit line, the ground line, P-well and the N-well may be discharged to ground.
Thereafter, the unselected state of the word line may be terminated, and the word line voltage may return to the neutral state. For example, the word line voltage may return to the power supply voltage Vcc, whereby the erase operation may be completed.
In such an erase operation, because the coupling capacitance between the word line and the bit line may be higher as illustrated in FIGS. 6 and 7, the bit line voltage may become higher due to the overshoot of the bit line voltage when discharging the word line voltage. Consequently, this higher bit line voltage may exceed a breakdown voltage of a component connected to the bit line and cause the component to fail.